8 Bit microcontroller compendium compiled by Roger Nelson This table consist of two parts: memory and pin counts, and features and peripherals. Manufacturer microcontroller descriptions often fail to summarize the microcontroller features in a way that allows one to quickly identify features across the full line. (Motorola used to have some neat pie/sector charts in the brown books (1987?)). This tabular crossreference is intended to serve as a quick lookup for a microcontroller that might have desired features for a particular application. For the Motorola line, refer to my mc68xx pinout guides to see a more detailed breakdown of the pin functions and port capabilities (the 6800, 6801, 6802, 6803, 6804, 6805, and 6811 families are cross referenced). Keep in mind that most of these microcontrollers operate in several modes. For example, in single chip mode, external memory expansion may not be available, or general purpose I/O lines may be replaced with memory address ports. Send additions, corrections, suggestions or comments to: Roger Nelson rnelson@mail.wsu.edu Blank entries are missing data the needs to be filled in. - entries indicate the processor does support this feature. Motorola Boot Exp TotalG.P.G.P. OTP EP EEP strp Mem I/O In Out I/O Tech Pins RAM ROM ROM ROM ROM mode (k) pins linelineline 6800 HMOS 40 - - - - - - 64 6801 HMOS 40 128 2048 - - - 64 29 6803 HMOS 40 128 - - - - 64 13 6801u4 HMOS 40 192 4096 - - - 64 29 6803u4 HMOS 40 192 - - - - 64 13 68701 HMOS 40 128 - - 2048 - 64 29 68701u4 HMOS 40 192 - - 4096 - 64 29 6802 HMOS - 64 6804j1 HMOS 20 30 512 - - - 0 12 6804j2 HMOS 20 30 1000 - - - 0 12 6804p2 HMOS 28 30 1016 - - - 0 20 68704p2 HMOS 28 30 - - 1020 - 0 20 68hc04j2 HCMOS 20 172 1000 - - - 0 12 68hc04j3 HCMOS 20 30 1672 - - - 0 12 68hc04p4 HCMOS 28 172 3700 - - - 0 20 68hc704p4 HCMOS 28 172 - - 3700 - 0 20 6805p2 HMOS 28 64 1110 - - - 0 20 6805p6 HMOS 28 64 1804 - - - 0 20 6805r3 HMOS 40/44 112 3776 - - - 0 32 6805s2 HMOS 28 64 1480 - - - 0 21 6805s3 HMOS 28 104 3720 - - - 0 21 6805u2 HMOS 40/44 64 2048 - - - 0 32 6805u3 HMOS 40/44 112 3376 - - - 0 32 68705p3 HMOS 28 112 - - 1804 - 0 20 68705p5 HMOS 28 112 - - 1804 - 0 20 68705r3 HMOS 40 112 - - 3776 - 0 32 68705r5 HMOS 40 112 - - 3776 - 0 32 68705s3 HMOS 28 104 - - 3752 - 0 21 68705u3 HMOS 40 112 - - 3776 - 0 32 68705u5 HMOS 40 112 - - 3776 - 0 32 68hc05a6 HCMOS40/44 176 4160 - - 2056 0 32 68hc05b4 HCMOS48/52 176 4160 - - - 0 32 68hc05b6 HCMOS40/52 176 5952 - - 256 0 32 68hc05c2 HCMOS 40 176 2096 - - - 0 32 68hc05c3 HCMOS 40 176 2096 - - - 0 32 68hc05c4 HCMOS40/44 176 4160 - - - 0 32 68hc05c8 HCMOS40/44 176 7700 - - - 0 32 68hc05c9 HCMOS 176 - - - 0 32 68hc05l6 HCMOS 68 176 6208 - - - 0 32 68hc05m4 HCMOS 52 128 4096 - - - 0 32 68hc05p1 HCMOS - - - 0 32 68hcl05c4 HCMOS40/44 176 4160 - - - 0 32 68hcl05c8 HCMOS40/44 176 8192 - - - 0 32 68hsc05c4 HCMOS40/44 176 4160 - - - 0 32 68hsc05c8 HCMOS40/44 176 8192 - - - 0 32 68hc705b5 HCMOS48/52 176 - - - - 0 32 68hc705c4 HCMOS40/44 176 - - - 0 32 68hc705c8 HCMOS40/44 304 - - - - 0 32 68hc805b6 HCMOS48/52 176 - - 8k 6208 0 32 68hc805c4 HCMOS40/44 176 - - - 4160 0 32 146805e2 CMOS 40 112 0 - - - 64 16 146805f2 CMOS 28 64 1089 - - - 64 20 146805g2 CMOS 40 112 2106 - - - 64 32 6809 HMOS 64 6809e HMOS 64 6810 HMOS 64 68hc11a0 HCMOS48/52 256 - - - - 64 38 68hc11a1 HCMOS48/52 256 - - - 512 y 64 38 68hc11a8 HCMOS48/52 256 8192 - - 512 y 64 38 68hc11d3 HCMOS40/44 192 4096 - - - y 64 30 68hc11e1 HCMOS 52 512 0 - - 512 y 64 38 68hc11e9 HCMOS 52 512 12k - - 512 y 64 38 68hc11f1 HCMOS - - - - y 64 - 68hc11d3 HCMOS 192 - - - y 64 38 68hc11e2 HCMOS48/52 256 - - - 2048 y 64 38 68hc705c8 HCMOS40/44 304 - 7616 - - 64 24 68hc711d3 HCMOS40/44 192 - 4096 - - 64 24 68hc711a8 HCMOS 52 256 - 8192 - - 64 38 68hc711e9 HCMOS48/52 512 - 12k - - 64 38 Although the expanded multiplex mode of the 68HC11 RAM memory expansion to 64k uses 16 output pins for addressing (2 8 bit ports), the MC68HC24 peripheral chip allows the processor to address 64k external memory while preserving the two I/O ports. Intel MCS family Exp TotalG.P.G.P. OTP EP EEP Boot Mem I/O In Out I/O Tech Pins RAM ROM ROM ROM ROM ROM (k) pins linelineline 8051 HMOS 128 4k - - - 64 8031 HMOS 128 - - - - 64 8051AH HMOS 128 4k - - - 64 8031AH HMOS 128 - - - - 64 8751H HMOS 128 4k - y? - 64 8751BH HMOS 128 4k - y? - 64 8052AH HMOS 256 8k - - - 64 8032AH HMOS 256 - - - - 64 8752BH HMOS 256 8k - y? - 64 80C51BH HMOS 128 4k - - - 64 80C31BH HMOS 128 - - - - 64 87C51 HMOS 128 4k - y? - 64 83C51FA HMOS 256 8k - - - 64 80C51FA HMOS 256 - - - - 64 87C51FA HMOS 256 8k - y? - 64 83C51FB HMOS 256 16k - - - 64 80C51FA HMOS 256 - - - - 64 87C51FB HMOS 256 16k - y? - 64 83C51GA HMOS 128 4k - - - 64 80C51GA HMOS 128 - - - - 64 87C51GA HMOS 128 4k - y? - 64 83C152JA HMOS 256 8k - - - 64 80C152JA HMOS 256 - - - - 64 80C152JB HMOS 256 - - - - 64 83C152JC HMOS 256 8k - - - 64 80C152JC HMOS 256 - - - - 64 80C152JD HMOS 256 - - - 64 83C451 HMOS 128 4k - - - 64 80C451 HMOS 128 - - - - 64 83C452 HMOS 256 8k - - - 64 80C452 HMOS 256 - - - - 64 87C452P HMOS 256 8k - y? - 64 Texas Instruments TMS370 Exp TotalG.P.G.P. OTP EP EEP Boot Mem I/O In Out I/O Tech Pins RAM ROM ROM ROM ROM ROM (k) pins linelineline 370C010 ? 28 128 4k - - - ? - 22 1 0 21 370C050 ? 68 256 4k - - - ? 112 55 9 0 46 370C032 ? 44 256 8k - - - ? - 36 13 9 14 370C052 ? 68 256 8k - - - ? 112 55 9 0 46 370C056 ? 68 512 16k - - - ? 112 55 9 0 46 370C310 ? 28 128 4k - - - ? - 22 1 0 21 370C350 ? 68 256 4k - - - ? 112 55 9 0 46 370C332 ? 44 256 8k - - - ? - 36 13 9 14 370C352 ? 68 256 8k - - - ? 112 55 9 0 46 370C356 ? 68 512 16k - - - ? 112 55 9 0 46 370C150 ? 68 256 - - - - ? 112 55 9 0 46 370C250 ? 68 256 - - - - ? 112 55 9 0 46 370C156 ? 68 512 - - - - ? 112 55 9 0 46 370C256 ? 68 512 - - - - ? 112 55 9 0 46 370C810 ? 28 128 - - - 4k ? - 22 1 0 21 370C850 ? 68 256 - - - 4k ? 112 55 9 0 46 370C732 ? 44 256 - - 8k - ? - 36 13 9 14 370C756 ? 68 512 - - 16k - ? 112 55 9 0 46 The Texas Instruments TMS370 series have either a 256 byte EEPROM (the 370Cx56 models have a 512 byte EEPROM) for data memory with the exception of the TMS3703xx which have none. National Semiconductor COP800 Exp TotalG.P.G.P. OTP EP EEP Boot Mem I/O In Out I/O Tech Pins RAM ROM ROM ROM ROM ROM (k) pins linelineline 800C MCMOS 820C MCMOS 28 64 1k - - - 32 24 821C MCMOS 24 64 1k - - - 20 822C MCMOS 20 64 1k - - - 16 840C MCMOS 28 128 2k - - - 32 24 841C MCMOS 24 128 2k - - - 20 842C MCMOS 20 128 2k - - - 16 620C MCMOS 28 64 1k - - - 24 621C MCMOS 24 64 1k - - - 20 622C MCMOS 20 64 1k - - - 16 640C MCMOS 28 128 2k - - - 24 641C MCMOS 24 128 2k - - - 20 642C MCMOS 20 128 2k - - - 16 820CB MCMOS 821CB MCMOS 822CB MCMOS 8640C MCMOS 28 64 2k - - 64 24 8641C MCMOS 24 64 2k - - 64 20 8642C MCMOS 20 64 2k - - 64 16 8620C MCMOS 28 64 1k - - 64 24 8621C MCMOS 24 64 1k - - 64 20 8622C MCMOS 20 64 1k - - 64 16 8720C MCMOS 28 64 1k - - 64 24 8721C MCMOS 24 64 1k - - 64 20 8722C MCMOS 20 64 1k - - 64 16 880 MCMOS 888CF MCMOS40/44 128 4k - - - 32 33/37 888CG MCMOS40/44 192 4k - - - 35/3 9 888CL MCMOS40/44 128 4k - - - 32 33/39 820CP-X MCMOS 840CP-X MCMOS 888CLP MCMOS28/40 128 - 884CLP MCMOS28/40 128 - 888CFP MCMOS28/40 128 - 21/33 884CFP MCMOS28/40 128 - 21/33 888CGP MCMOS28/40 192 - 23/35 884CGP MCMOS28/40 192 - 23/35 888CLMH MCMOS 44 128 - 8k 37 888CFMH MCMOS 44 128 - 8k 37 888CGMH MCMOS 44 192 - 8k 39 The ports D and L are used to address external memory in ROMless mode. __________________________________________________________________________ A/D converters are provided on several microcontroller models. In some models an interrupt is generated when the conversion is complete in others, the program must wait for a conversion to complete (MC68xx). Some microcontrollers may not have A/D converters, but may have simpler differential comparators (com). Interrupt sources/vectors. Some of the sources may be dedicated to processor functions such as: software traps, timer functions, serial device, wake up or watch dog functions. Memory mapped I/O. All the processor listed here use memory mapped I/O. The watch dog timer can be used to catch programs that get stuck in infinate loops. The w.d.t may reset the processor and external system. Computer operating properly will reset the system if the clock rate falls below operating limits. The 8/16/32 bit timers may have modes which allow them to clock events internally or externally, refer to the chip's data book. Some controllers such as the MC6811 series have a special pulse accumulator which allows a counter to be incremented on rising or falling (selectable) edges without have to interrupt the program. The program can pull the counter register for the current value, the N.S. COP family allows the timer to be programmed for this functionality. Syncronous serial ports are often used to communicate with other peripherals using syncronous serial protocols such as memory servers, display drivers, additional A/D ports, etc., or a simple network of micro controllers in a master/slave configuration. This allows communication with these devices using just a few pins without taking 2 or 3 data/address ports for memory mapped I/O. The SPI is a syncronous serial port (serial peripheral interface) The SPI doesn't require start/stop bits and can operate at higher clock rates. The MicroWire/Plus in the National Semiconductor family is a syncronous serial port similar to an SPI. Asyncronous serial ports are often configured to be used as an RS-232 port. The SCI is a asyncronous serial port (serial communication interface) This port can be configured for communication with an RS-232 port by providing the necessary voltage augmentation such as a MAX233 chip. The UART is an asyncronous serial port similar to the SCI, but it is double buffered (2 bytes) allowing for faster operation with less chance for overrun errors. SCI and UART functions may feature an (attention or wake up mode) which monitors the input for an address character (flagged by bit 9 set). An interrupt is generated where the program may determine based on the address value to receive the following input data. Keep in mind that the SCI and UART are not identical devices; also, SCI capabilities may vary within a family line. Motorola Int Mem Wch Min Bus 8 16 32 A/D src map dog clk spd NMI Msk bit bit bit Pls Chn vct I/O tmr rate Mhz SPC SCI Int Int tim tim tim acc. 6800 - y 6801 - y - y - 1 - 6803 - y - y - 1 - 6801u4 - y - y - 1 - 6803u4 - y - y - 1 - 68701 - y - y - 1 - 68701u4 - y - y - 1 - 6802 - y - - - 6804j1 - y 1 - - 6804j2 - y 1 - - 6804p2 - y 1 - - 68704p2 - y 1 - - 68hc04j2 - y 1 - - 68hc04j3 - y 1 - - 68hc04p4 - y 1 - - 68hc704p4 - y 1 - - 6805p2 - y - 1 - - 4 6805p6 - y - 1 - - 4 6805r3 4 y - 1 - - 4 6805s2 4 y y 1 - - 4 6805s3 4 y y 1 - - 4 6805u2 4 y y 1 - - 4 6805u3 - y - 1 - - 4 68075p3 - y - 1 - - 4 68705p5 - y - 1 - - 68705r3 - y - 1 - - 68705r5 4 y - 1 - - 68705s3 4 y - 1 - - 68705u3 4 y y 2 1 - 68705u5 - y - 1 - - 68hc05a6 - y - 1 - - 4 68hc05b4 - y y y 1 - 4 68hc05b6 4 y - y 1 - 4 68hc05c2 4 y - y 1 - 4 68hc05c3 - y - - 1 - 4 68hc05c4 - y y y 1 - 4 68hc05c8 - y y y 1 - 4 68hc05c9 - y y y 1 - 4 68hc05l6 - y y y 1 - 4 68hc05m4 - y y - 1 - 4 68hc05p1 6 y - - 1 1 - 4 68hcl05c4 - y y y 1 - 4 68hcl05c8 - y y y 1 - 4 68hsc05c4 - y y y 1 - 4 68hsc05c8 - y y y 1 - 4 68hc705b5 - y y y 1 - 68hc705c4 - y y y 1 - 68hc705c8 - y y y 1 - 68hc805b6 - y y y 1 - 68hc805c4 - y - y 1 - 146805e2 - y y y 1 - 146805f2 - y - - 1 - 146805g2 - y - - 1 - 6809 - y - - 1 - 6809e - y - 6810 - y - 68hc11a0 8 y y y 1 68hc11a1 8 y y y 1 68hc11a8 8 y y y 1 68hc11d3 - y - y 1 68hc11e1 8 y y y 1 68hc11e9 8 y y y 1 68hc11f1 8 y - - 1 68hc11d3 - y y y 1 68hc11e2 8 y y y 1 68hc705c8 - y y y 68hc711d3 - y y y 68hc711a8 y y y y 68hc711e9 y y y y 68hc811e2 8 y y y Since no interrupt is generated at the completion of an A/D conversion, the data registers must be polled. The 680x series SCI has fixed baud rate, the 6811 series offers the addition of software selectable baud rates and interrupt drive operation. Intel MCS family Int Mem Wch Min Bus S G Timer/pulse A/D src map dog clk spd E S NMI Msk accumulator Pls Chn vct I/O tmr rate Mhz P P UARTInt Int 9 16 32 acc. 8051 - 6/5 y y - - y - 2 - 8031 - 6/5 y y - - y - 2 - 8051AH - 6/5 y y - - y - 2 - 8031AH - 6/5 y y - - y - 2 - 8751H - 6/5 y y - - y - 2 - 8751BH - 6/5 y y - - n? - 2 - 8052AH - 8/6 y y - - y - 3 - 8032AH - 8/6 y y - - y - 3 - 8752BH - 8/6 y y - - y - 3 - 80C51BH - 6/5 y y - - y - 2 - 80C31BH - 6/5 y y - - y - 2 - 87C51 - 6/5 y y - - y - 2 - 83C51FA - 14/7 y y - - y - 3 - 80C51FA - 14/7 y y - - y - 3 - 87C51FA - 14/7 y y - - y - 3 - 83C51FB - 14/7 y y - - y - 3 - 80C51FA - 14/7 y y - - y - 3 - 87C51FB - 14/7 y y - y - 3 - 83C51GA 8 8/7 y y y - y - 2 - 80C51GA 8 8/7 y y y - y - 2 - 87C51GA 8 8/7 y y y - y - 2 - 83C152JA - 19/11 y y - y y - 2 - 80C152JA - 19/11 y y - y y - 2 - 80C152JB - 19/11 y y - y y - 2 - 83C152JC - 19/11 y y - y y - 2 - 80C152JC - 19/11 y y - y y - 2 - 80C152JD - 19/11 y y - y y - 2 - 83C451 - 6/5 y y - - y - 2 - 80C451 - 6/5 y y - - y - 2 - 83C452 - 9/8 y y - - y - 2 - 80C452 - 9/8 y y - - y - 2 - 87C452P - 9/8 y y - - y - 2 - * Depending on the selected mode, Each timer may be either one 8bit, or one 16bit or 2 8bit timers. The UART is double buffered The A/D conversion generates an interrupt Texas Instruments TMS370 series Int Mem Wch Min Bus 8 16 32 A/D src map dog clk spd NMI Msk bit bit bit Pls Chn vct I/O tmr rate Mhz SPC SCI Int Int tim tim tim acc. 370C010 - 6/13 y y 2-20 y - ? ? ? ? ? 370C050 8 10/23 y y 2-20 y y ? ? ? ? ? 370C032 8 23/25 y pact2-20 pact y ? ? ? ? ? 370C052 8 10/23 y y 2-20 y y ? ? ? ? ? 370C056 8 10/23 y y 2-20 y y ? ? ? ? ? 370C310 - 6/13 y y 2-20 y - ? ? ? ? ? 370C350 8 10/23 y y 2-20 y y ? ? ? ? ? 370C332 8 23/25 y 2-20 pact y ? ? ? ? ? 370C352 8 10/23 y y 2-20 y y ? ? ? ? ? 370C356 8 10/23 y y 2-20 y y ? ? ? ? ? 370C150 8 10/23 y y 2-20 y y ? ? ? ? ? 370C250 8 10/23 y y 2-20 y y ? ? ? ? ? 370C156 8 10/23 y y 2-20 y y ? ? ? ? ? 370C256 8 10/23 y y 2-20 y y ? ? ? ? ? 370C810 - 6/13 y y 2-20 y - ? ? ? ? ? 370C850 8 10/23 y pact2-20 y y ? ? ? ? ? 370C732 8 23/25 y y 2-20 pact y ? ? ? ? ? 370C756 8 10/23 y y 2-20 y y ? ? ? ? ? The TI A/D system only has one data register, thus only one conversion can be done at a time. I'm not sure if the pact is built in to the microcontroller or is offered as peripheral component. National Semiconductor Int Mem Wch Min Bus Micro 8 16 32 A/D src map dog clk spd wire NMI Msk bit bit bit Pls Chn vct I/O tmr rate Mhz ser UARTInt Int tim tim tim acc. 800C y y - 1 - 820C - 3 y y - 1 - 821C - 3 y y - 1 - 822C - 3 y y - 1 - 840C - 3 y y - 1 - 841C - 3 y y - 1 - 842C - 3 y y - 1 - 620C - 3 y y - 1 - 621C - 3 y y - 1 - 622C - 3 y y - 1 - 640C - 3 y y - 1 - 641C - 3 y y - 1 - 642C - 3 y y - 1 - 820CB y y 821CB y y 822CB y y 8640C - 3 y y - 1 - 8641C - 3 y y - 1 - 8642C - 3 y y - 1 - 8620C - 3 y y - 1 - 8621C - 3 y y - 1 - 8622C - 3 y y - 1 - 8720C - 3 y y - 1 - 8721C - 3 y y - 1 - 8722C - 3 y y - 1 - 880 - ? y - y - 1 - 888CL - 10 y y y - 1 - 888CF 8 10 y y - 2 - 888CG - 14 y y y - 3 - 820CP-X y y 840CP-X y y 888CLP 10 y y y - 2 - 884CLP 10 y y y - 2 - 888CFP 8 10 y y y - 2 - 884CFP 8 10 y y y - 2 - 888CGP 2com14 y y yp y - 3 - 884CGP 2com14 y y yp y - 3 - 888CLMH - 10 y y y - - 2 - 888CFMH 8 10 y y y y - 2 - 888CGMH 2com14 y y yp y - 3 - The N.S. timers have three modes of operation: 1 - Processor independent mode: once operation parameter have been setup output signals are generated automatically without additional program intervation when the timer counts down to 0 (underflow). 2 - External event counter mode: The timer counts pulse event on an input pin and generates and interrupt when the timer counts down to 0. 3 - Input Capture mode: The timer counts at a fixed rate, when a pulse event occurs on an input pin, the current counter value is copied to a timer register and an interrupt is generated. References: Motorolla Microprocessor, Microcontroller and Peripheral Databook vols. I and II (1988) National Semiconductor Microcontroller Databook (1989) Hitz, Kenneth and Tabak, Daniel Microcontrollers: Architecture, Implementation , & Programming McGraw-Hill Inc. 1992