DS1211 1-of-8 inverting decoder/nonvolatile SRAM controller chip. TOL selects power-fail VCC level, based on 5% tolerance when 0 or 10% tolerance when 1. The Dallas data book suggests this is actually a repackaged DS1212. +----------+ +----------------------------------------+ VBAT1 |1 +--+ 20| VCC |/EN| S2| S1| S0|VCC |/Y0|/Y1|...|/Y7|/PF| VCCo |2 19| VBAT2 |---+---+---+---+----+---+---+---+---+---| TOL |3 18| /EN | X | X | X | X | LO | 1 | 1 | 1 | 1 | 0 | /PF |4 17| /Y0 | 1 | 0 | 0 | 0 | OK | 0 | 1 | 1 | 1 | 1 | /Y7 |5 DS 16| /Y1 | 0 | 0 | 0 | 1 | OK | 1 | 0 | 1 | 1 | 1 | /Y6 |6 1211 15| /Y2 | 0 | . | . | . | OK | 1 | 1 | . | 1 | 1 | S2 |7 14| /Y3 | 0 | 1 | 1 | 1 | OK | 1 | 1 | 1 | 0 | 1 | S1 |8 13| +----------------------------------------+ S0 |9 12| /Y4 GND |10 11| /Y5 +----------+ [This information is part of the GIICM]