DS1212
1-of-16 inverting decoder/nonvolatile SRAM controller chip.
TOL selects power-fail VCC level, based on 5% tolerance when 0 or
10% tolerance when 1.

      +--------------+        +---------------------------------------------+
VBAT1 |1    +--+   28| VCC    |/EN| S3| S2| S1| S0|VCC |/Y0|/Y1|...|/Y15|/PF|
 VCCo |2           27| VBAT2  |---+---+---+---+---+----+---+---+---+----+---|
  TOL |3           26| /EN    | X | X | X | X | X | LO | 1 | 1 | 1 | 1  | 0 |
  /PF |4           25| /Y0    | 1 | 0 | 0 | 0 | 0 | OK | 0 | 1 | 1 | 1  | 1 |
 /Y15 |5           24| /Y1    | 0 | 0 | 0 | 0 | 1 | OK | 1 | 0 | 1 | 1  | 1 |
 /Y14 |6           23| /Y2    | 0 | . | . | . | . | OK | 1 | 1 | . | 1  | 1 |
 /Y13 |7     DS    22| /Y3    | 0 | 1 | 1 | 1 | 1 | OK | 1 | 1 | 1 | 0  | 1 |
 /Y12 |8    1212   21| /Y4    +---------------------------------------------+
 /Y11 |9           20| /Y5
   S3 |10          19| /Y6
   S2 |11          18| /Y7
   S1 |12          17| /Y8
   S0 |13          16| /Y9
  GND |14          15| /Y10
      +--------------+

[This information is part of the GIICM]