63705 63705 registers 19900420/wjvg 00 rw port a 01 rw port b 02 rw port c 03 rw port d 04 rw port a direction, 1=output 05 rw port b direction, 1=output 06 rw port c direction, 1=output 07 rw port d direction, 1=output 08 rw timer data 09 timer control rw 1....... timer interrupt request rw .1...... disable timer interrupt rw ..00.... timer source = e-clock rw ..01.... timer source = and of external clock and e-clock rw ..10.... timer source = no clock rw ..11.... timer source = external clock r ....0... always w ....1... clear prescaler rw .....nnn prescaler is 2^n (1..128) 0a miscellaneous r 1....... int2 request w 0....... reset int2 request rw .1...... disable int2 interrupt rw ..1..... set edge+level/edge-only sensitive interrupt r ...11111 not used 10 sci control rw 1....... port_d3: serial-out rw .1...... port_d4: serial-in rw ..0x.... port_d5: normal-io rw ..10.... port_d5: clock-out rw ..11.... port_d5: clock-in rw ....nnnn transfer clock width is 2^n us (at 4 MHz) (1..32768 us) 11 sci status r 1....... sci interrupt request (auto clear at data read/write) w 0....... clear sci interrupt request r .1...... timer2 interrupt request w .0...... clear timer2 interrupt request rw ..1..... disable sci interrupt rw ...1.... disable timer2 interrupt r ....0... always w ....1... clear prescaler 12 rw sci data end