su8 super 8 registers 19890330/wjvg system registers - d0 208 p0 port0 - d1 209 p1 port1 - d2 210 p2 port2 - d3 211 p3 port3 - d4 212 p4 port4 - d5 213 flags program control flags (system flags register) rw 1....... carry flag rw .1...... zero flag rw ..1..... sign flag rw ...1.... overflow flag rw ....1... decimal adjust rw .....1.. half-carry flag rw ......1. fast interrupt status rw .......1 bank address - d6 214 rp0 register pointer 0 xxxxx... - d7 215 rp1 register pointer 1 xxxxx... - d8 216 sph stack pointer high - d9 217 spl stack pointer low - da 218 iph instruction pointer high - db 219 ipl instruction pointer low - dc 220 irq interrupt request register r 1....... level7 r .1...... level6 r ..1..... level5 r ...1.... level4 r ....1... level3 r .....1.. level2 r ......1. level1 r .......1 level0 - dd 221 imr interrupt mask register rw 1....... level7 rw .1...... level6 rw ..1..... level5 rw ...1.... level4 rw ....1... level3 rw .....1.. level2 rw ......1. level1 rw .......1 level0 - de 222 sym system mode rw xxx..... not used rw ...xxx.. fast interrupt level select rw ......1. fast interrupt enable rw .......1 global interrupt enable - df 223 ??? bank0 registers 0 e0 224 c0ct counter 0 control 0 e1 225 c1ct counter 1 control rw 1....... continuous/single cycle rw .1...... count up/down rw ..1..... load counter rw ...1.... software trigger rw ....1... software capture rw .....1.. zero count interrupt enable r ......1. end of count w ......1. reset end of count rw .......1 enable counter 0 e2 226 c0ch counter 0 capture high 0 e3 227 c0cl counter 0 capture low 0 e4 228 c1ch counter 1 capture high 0 e5 229 c1cl counter 1 capture low 0 e6 230 ??? 0 e7 231 ??? 0 e8 232 ??? 0 e9 233 ??? 0 ea 234 ??? 0 eb 235 utc uart transmit control rw 1....... transmit on p31 rw .1...... send break rw ..1..... 2/1 stop bits rw ...1.... wake-up enable rw ....1... transmit enable r .....1.. brg zero count w .....1.. brg zero count reset rw ......1. transmit buffer empty rw .......1 transmit dma enable 0 ec 236 urc uart receive control r 1....... wake-up detect | r .1...... control character detect | r ..1..... break detect | r ...1.... framing error | r ....1... overrun error | these bits can be reset, r .....1.. parity error | by writing a 1 there w ......1. receive enable r .......1 receive character available 0 ed 237 uie uart interrupt enable rw 1....... wake-up interrupt enable rw .1...... control character interrupt enable rw ..1..... break interrupt enable rw ...1.... receive error interrupt enable rw ....1... zero count interrupt enable rw .....1.. transmit interrupt enable rw ......1. receive dma enable rw .......1 receive character available interrupt enable 0 ee 238 ??? 0 ef 239 uio uart data 0 f0 240 p0m port 0 mode per bit: address/io 0 f1 241 pm port mode w xx...... not used w ..00.... output w ..01.... input w ..1x.... address/data w ....1... dm on p35 w .....1.. open-drain/push-pull port 1 w ......1. open-drain/push-pull port 0 w .......1 port 0 input/output 0 f2 242 ??? 0 f3 243 ??? 0 f4 244 h0c handshake 0 control w xxxx.... deskew counter w ....1... fully-interlocked/strobed w .....1.. dma enable w ......1. port 1/4 select w .......1 handshake enable 0 f5 245 h1c handshake 1 control w xxxx.... deskew counter w ....1... fully-interlocked/strobed w .....xx. not used w .......1 handshake enable 0 f6 246 p4d port 4 direction per bit: input/output 0 f7 247 p4od port 4 mode per bit: open-drain/push-pull 0 f8 248 p2am port 2/3a mode w xx...... p31 mode w ..xx.... p30 mode w ....xx.. p21 mode w ......xx p20 mode 0 f9 249 p2bm port 2/3b mode w xx...... p33 mode w ..xx.... p32 mode w ....xx.. p23 mode w ......xx p22 mode 0 fa 250 p2cm port 2/3c mode w xx...... p35 mode w ..xx.... p34 mode w ....xx.. p25 mode w ......xx p24 mode 0 fb 251 p2dm port 2/3d mode w xx...... p37 mode w ..xx.... p36 mode w ....xx.. p27 mode w ......xx p26 mode w ......00 input w ......01 input, interrupt enabled w ......10 output, push-pull w ......11 output, open-drain 0 fc 252 p2aip port 2/3a interrupt pending r 1....... p33 interrupt pending, miw: 7720.1 r .1...... p32 interrupt pending, miw: 7720.0, fdc irq r ..1..... p23 interrupt pending r ...1.... p22 interrupt pending, miw: dtmf irq r ....1... p31 interrupt pending r .....1.. p30 interrupt pending r ......1. p21 interrupt pending r .......1 p20 interrupt pending 0 fd 253 p2bip port 2/3b interrupt pending r 1....... p37 interrupt pending r .1...... p36 interrupt pending r ..1..... p27 interrupt pending, miw: ring detect r ...1.... p26 interrupt pending, miw: hook detect r ....1... p35 interrupt pending r .....1.. p34 interrupt pending, miw: floppy dreq r ......1. p25 interrupt pending r .......1 p24 interrupt pending 0 fe 254 emt external memory timing rw 1....... p34 is /wait-input rw .1...... slow memory timing enable rw ..xx.... number of program memory wait states, werkt niet! rw ....xx.. number of data memory wait states, werkt niet! rw ......1. stack in data memory/register file rw .......1 dma in data memory/register file 0 ff 255 ipr interrupt priority register rw 0..0..0. undefined rw 0..0..1. b>c>a rw 0..1..0. a>b>c rw 0..1..1. b>a>c rw 1..0..0. c>a>b rw 1..0..1. c>b>a rw 1..1..0. a>c>b rw 1..1..1. undefined rw .1...... c: 7>6 rw ..1..... c: 67>5 rw ....1... b: 4>3 rw .....1.. b: 34>2 rw .......1 a: 1>0 bank1 registers 1 e0 224 c0m counter 0 mode, n=2 1 e1 225 c1m counter 1 mode, n=3 pn7 pn6 rw 0000.... io io rw 0001.... io trigger rw 0010.... gate io rw 0011.... gate trigger rw 0100.... io c0 input rw 0101.... trigger c0 input rw 0110.... gate c0 input rw 0111.... gate/trigger c0 input rw 1000.... c0 output io rw 1001.... c0 output trigger rw 1010.... c0 output gate rw 1011.... c0 output gate/trigger rw 1100.... c0 output c0 input rw 1101.... undefined rw 1110.... undefined rw 1111.... cascade counters rw ....1... enable retrigger rw .....1.. programmed/pn7 up/down control rw ......00 no capture rw ......01 capture on rising edge of pn7 rw ......10 bi-value mode rw ......11 capture on both edges of pn7 1 e2 226 c0tch counter 0 time constant high 1 e3 227 c0tcl counter 0 time constant low 1 e4 228 c1tch counter 1 time constant high 1 e5 229 c1tcl counter 1 time constant low 1 e6 230 ??? 1 e7 231 ??? 1 e8 232 ??? 1 e9 233 ??? 1 ea 234 ??? 1 eb 235 ??? 1 ec 236 ??? 1 ed 237 ??? 1 ee 238 ??? 1 ef 239 ??? 1 f0 240 dch dma count high, het adres staat in c0h en c1h! (rr0) 1 f1 241 dcl dma count low 1 f2 242 ??? 1 f3 243 ??? 1 f4 244 ??? 1 f5 245 ??? 1 f6 246 ??? 1 f7 247 ??? 1 f8 248 ubgh uart baud rate generator high 1 f9 249 ubgl uart baud rate generator low 1 fa 250 uma uart mode a rw 00...... clock rate /1 rw 01...... clock rate /16 rw 10...... clock rate /32 rw 11...... clock rate /64 rw ..00.... 5 bits rw ..01.... 6 bits rw ..10.... 7 bits rw ..11.... 8 bits rw ....1... parity enable rw .....1.. even parity rw ......1. receive wake-up value rw .......1 transmit wake-up value 1 fb 251 umb uart mode b rw 00...... clock output is p21 data rw 01...... clock output is system clock (xtal/2) rw 10...... clock output is baud-rate generator output rw 11...... clock output is transmit data clock rw ..1..... auto echo rw ...1.... receive clock input is baud-rate generator output/p20 rw ....1... transmit clock input is baud-rate generator output/p21 rw .....1.. baud-rate generator source is (xtal/4)/p20 rw ......1. baud-rate generator enable rw .......1 loopback enable 1 fc 252 ??? 1 fd 253 ??? 1 fe 254 wumch wake-up match 1 ff 255 wumsk wake-up mask, and'ed with uart data before comparing end