VESA LOCAL BUS (VLB) This file is intended to provide a basic functional overview of the Vesa Local Bus, so that hobbyists and ametuers can design their own VLB compatible cards. It is not intended to provide complete coverage of the VLB standard. VLB Connectors are usually inline with ISA connectors, so that adapter cards may use both. However, the VLB is seperate, and does not need to connect to the ISA portion of the bus. Pinouts: 64 Bit Side B Pin Side A 64 Bit Signals (Optional) D0 01 D1 (Optional) D2 D3 D4 GND D6 D5 D8 D7 GND D9 D10 D11 D12 D13 VCC D15 D14 10 GND D16 D17 D18 VCC D20 D19 GND D21 D22 D23 D24 D25 D26 GND D28 D27 D30 D29 VCC 20 D31 D63 A31 A30 D62 GND A28 D60 D61 A29 A26 D58 D59 A27 GND D57 A25 A24 D56 D55 A23 A22 D54 D53 A21 VCC D51 A19 A20 D52 GND A18 D50 D49 A17 30 A16 D48 D47 A15 A14 D46 VCC A12 D44 D45 A13 A10 D42 D43 A11 A8 D40 D41 A9 GND D39 A7 A6 D38 D37 A5 A4 D36 GND *WBACK D35 A3 *BEO *BE4 D34 A2 40 VCC *LBS64 n/c *BE1 *BE5 *RESET *BE2 *BE6 D/C GND D33 M/IO *BE3 *BE7 D32 W/R 45 *ADS KEY (46-47) *RDYRTN 48 *LRDY GND *LDEV IRQ9 50 *LREQ *BRDY GND *BLAST *LGNT ID0 VCC ID1 ID2 GND ID3 LCLK ID4 *ACK64 VCC *LKEN *LBS16 58 *LEADS * indicates Active Low The 64 bit expansion of the bus (optional) does not add additional pins or connectors. Instead, it multiplexes the existing pins. The 32 bit VLB bus does not use the 64 bit signals shown in the above pinouts. A2-A31: Address Bus *ADS: Address Strobe *BE0-*BE3: Byte Enable. Indicates that the 8 data lines corresponding to each signal will deliver valid data. *BLAST: Burst Last. Indicates a VLB Burst Cycle, which will complete with *BRDY. The VLB Burst cycle consists of an address phase followed by four data phases. *BRDY: Burst Ready. Indicates the end of the current burst transfer. D0-D31: Data Bus. Valid bytes are indicated by *BE(x) signals. D/C: Data/Command. Used with M/IO and W/R to indicate the type of cycle. M/IO D/C W/R 0 0 0 INTA sequence 0 0 1 Halt/Special (486) 0 1 0 I/O Read 0 1 1 I/O Write 1 0 0 Instruction Fetch 1 0 1 Halt/Shutdown (386) 1 1 0 Memory Read 1 1 1 Memory Write ID0-ID4: Identification Signals. ID0 ID1 ID4 CPU Bus Width Burst 0 0 0 (res) 0 0 1 (res) 0 1 0 486 16/32 Burst Possible 0 1 1 486 16/32 Read Burst 1 0 0 386 16/32 None 1 0 1 386 16/32 None 1 1 0 (res) 1 1 1 486 16/32/64 Read/Write Burst ID2 Indicates wait: 0 = 1 wait cycle (min), 1 = no wait ID3 Indicates bus speed: 0 = greater than 33.3 MHz 1 = less than 33.3 MHz IRQ9: Interrupt Request. Connected to IRQ9 on ISA bus.This allows standalone VLB adapters (not connected to ISA portion of the bus) to have one IRQ. *LEADS: Local Enable Address Strobe. Set low by VLB master (not CPU). Also used for cache invalidation signal. *LBS16: Local Bus Size 16. Used by slave device to indicate that it has a transfer width of only 16 bits. LCLK: Local Clock. Runs at the same frequency as the cpu, up to 50 MHz. 66 MHz is allowed for on-board devices. *LDEV: Local Device: When appropriate address and M/IO signals are present on the bus, the VLB device must pull this line low to indicate that it is a VLB device. The VLB controller will then use the VLB bus for the transfer. *LRDY: Local Ready. Indicates that the VLB device has completed the cycle. This signal is only used for single cycle transfers. *BRDY is used for burst transfers. *LGNT: Local Grant. Indicates that an *LREQ signal has been granted, and control is being transferred to the new VLB master. *LREQ: Local Request. Used by VLB Master to gain control of the bus. M/IO: Memory/IO. See D/C for signal description. *RDYRTN: Ready Return. Indicates VLB cycle has been completed. May precede LRDY by one cycle. *RESET: Reset. Resets all VLB devices. *WBACK: Write Back. 64 BIT EXPANSION SIGNALS: *ACK64: Acknowledge 64 bit transfer. Indicates that the device can perform the requested 64 bit transfer cycle. *BE4-*BE7: Byte Enable. Indicates which bytes are valid (similar to *BE0-*BE3). D32-D63: Upper 32 bits of data bus. Multiplexed with address bus. *LBS64: Local Bus Size 64 bits. Used by VLB Master to indicate that it desires a 64 bit transfer. W/R: Write/Read. See D/C for signal description. 64 Bit Data Transfer Timing Diagram: Address Data Phase Phase _______ _______ _______ LCLK ___| |_______| |_______| |_______ ____ ______________________________________ *ADS |_______| _______________ _______________ A2-A31 ----<_______________><_______________>------------- D34-D63 Address Data D34-D63 _______________ _______________ D/C ----<_______________><_______________>------------- M/IO, W/R M/IO, W/R Data D32-33 _____ _____________________________ *LDEV |_______________| _____ _____________________________ *LBS64 |_______________| ______ _____________________________ *ACK64 |______________| _______________ D0-D31 --------------------<_______________>------------- _____________________ _____________ LRDY |______________| (C) Copyright 1996 by Mark Sokos. This file may be freely copied and distributed, as long as no fee is charged.The latest version of this file may be found at: http://users.desupernet.net/sokos/ E-mail questions or comments to sokos@desupernet.net. References: "The Indispensible PC Hardware Book" by Hans-Peter Messmer ISBN 0-201-8769-3