2060 programming the 2060 sicofi 19880312/wjvg registers: 0 status r: bit 7 is irq flag (1=ready for send/receive) 0 clrirq w: clear irq mask (disable irq's) 1 setirq w: set irq mask (enable irq's) 2 pwrdwn w: power down sicofi (set reset pin high) 3 pwr_up w: power up sicofi (set reset pin low) 4 voicea voice a channel data 5 voiceb voice b channel data 6 contrl control byte 7 signal signaling byte commando's voor het contrl register: w 11111111 nop w 1....... address info if 2 sicofi's are connected to one sld bus w .1...... read/write w ..1..... power-up/power-down sicofi w ...1.... three-party conferencing, received voicea and voiceb are added w ....01.. must be for sop command w ......00 status setting completed, no bytes following w ......01 set cr1 (followed by 1 byte for cr1) w ......10 set cr2 and cr1 (followed by 2 bytes for cr2 and cr1) w ..000011 B-filter coefficients part 1 (followed by 8 bytes of data) w ..001011 B-filter coefficients part 2 (followed by 8 bytes of data) w ..010011 Z-filter coefficients (followed by 8 bytes of data) w ..011000 B-filter delay coefficients (followed by 4 bytes of data) w ..100011 X-filter coefficients (followed by 8 bytes of data) w ..101011 R-filter coefficients (followed by 8 bytes of data) w ..110000 GX-, GR-filter coefficients (followed by 4 bytes of data) cr1: w 0....... enable b-filter (trans-hybrid balance filter, loopback) w .1...... enable z-filter (impedance matching filter, outside loopback) w ..1..... enable x-filter (gain frequency response adjust) w ...1.... enable r-filter (gain frequency response adjust) w ....1... enable gx en gr (gain frequency response adjusts) w .....000 no test mode w .1...001 analog loop back via z-filter w .....010 disable high pass w .....011 cut off receive path (hp active) w .....100 not used w .....101 not used w 0....110 digital loop back via b filter w .....111 digital loop back via pcm register cr2: w 1....... signaling pin sd is input/output w .1...... signaling pin sc is input/output w ..1..... signaling pin sb is input/output w ...1.... signaling pin sa is input/output w ....1... signaling expansion logic connected w .....1.. one sicofi connected to one pbc port (if am=0, sa is input aut.); w ......1. u-law/A-law filtering (u-law is european) w .......1 fixed/programmed filter coefficients for b-filter data-byte format w sddd.... coefficient 1 (s=sign, ddd=shift code 2^ddd) w ....sddd coefficient 2 (s=sign, ddd=shift code 2^ddd) note subsequent to reading the filter coefficients, cr2 and cr1 are transmitted additionally signaling byte: r 1....... si1 r .1...... si2 r ..1..... si3 r ...1.... sd r ....1... sc r .....1.. sb r ......1. sa r .......1 sel, signaling expansion bit if el=1 in cr2 w 1....... so1 w .1...... so2 w ..1..... so3 w ...1.... sd w ....1... sc w .....1.. sb w ......1. sa w .......1 sel, signaling expansion bit if el=1 in cr2 ,pg Operating modes Basic setting mode. Upon initial application of Vdd or during rs=1, the sicofi enters a basic setting mode: cr1=$00, cr2=$ff, sip=hi-Z, Vout=0, so1=so2=so3=0. The serial interface is ready to receive commands. Standby mode. Upon reception of a sop command (to load cr2), the sicofi enters the standby mode. The serial interface is ready to receive and transmit commands and data. Operating mode. From standby mode, the operating mode is entered upon recognition of a power-up bit (pu=1). The sicofi is reset to standby mode by power-down bit (pu=0) The filters contain (see commands sequence): ff5f 37a4 f65a ed99 beff 00ff ffff ffff __7$vZm_>_______ ff6e 2fdf d953 4055 3fff 00ff ffff ffff _n/_YS@U?_______ ffae 6bef aab3 98df efff 00ff ffff ffff _.ko*3__o_______ ff70 67fc fcff 00ff ffff 00ff ffff ffff _pg||___________ ffea 3eba b1b9 fbbd eaff 00ff ffff ffff _j>:19{=j_______ ff36 e135 f79c 0d4f 1fff 00ff ffff ffff _6a5w__O________ ffb5 b4e7 0cff 00ff ffff ffff ffff ffff _54g____________ The first 'ff' is erraneously read. *end