*386
*the registers and memory structures within the 386/486
*19920118/wj van ganswijk
*extended flags register (eflags)
fedcba98 76543210
0 0....... ........ must be 0
.1...... ........ back link available for current task
..ll.... ........ input/output and IF_flag_change maximum privilege level
....1... ........ overflow
.....1.. ........ direction
......1. ........ enable interrupts (may sometimes not be changed by user)
.......1 ........ enable single stepping traps
........ 1....... sign
........ .1...... zero
........ ...1.... auxiliary carry flag
........ .....1.. parity
........ .......1 carry
........ ..0.0.0. must be 0
2 ........ .....1.. give fault17 on alignment fault
........ ......1. enable virtual mode (8086)
........ .......1 skip breakpoint int on next instruction and change to 0
00000000 00000... must be 0
*segment descriptors, as pointed to by the gdtr, idtr and ldtr
*the first descriptor in the gdt must be empty
fedcba98 76543210
0 llllllll llllllll segment limit 15..0 (in granules) (aligned if pages)
2 bbbbbbbb bbbbbbbb segment base 15..0
4 bbbbbbbb segment base 23..16
5 1....... present
.pp..... privilige level
...10d.. data segment: expansion down/up segment
...10.w. data segment: segment may be written into
...11c.. code segment: conforming (only exe'ble if ..)
...11.r. code segment: readable
.......1 accessed
...0.001 system segment: tss, available
...0.011 system segment: tss, busy
....1... system segment: 486/80286 version
...00010 system segment: ldt
...0.1.. gate descriptor, see below
6 1....... 4kpage/byte granularity
.1...... 32/16 bits operation default (valid in code segment only)
..0..... must be 0
...1.... available for OS
....llll segment limit 19..16 (in granules)
7 bbbbbbbb base 31..24
*gate descriptor
*variatie op de segment descriptor, onderscheidbaar door het type in byte 5
fedcba98 76543210
0 oooooooo oooooooo offset within the target code segment 15..0
2 ssssssss ssssssss target code or task state segment selector
4 000..... must be 0
...ppppp parameter count 32/16 bit for 486/80286 gates
5 1....... valid
.ll..... maximum allowed level of caller
...1.... data segment, see above
...0.0.. system segment, see above
...0.100 call gate
...00101 task gate (80286 or 486)
...0.110 interrupt gate
...0.111 trap gate
....1... 486/80286 version
6 oooooooo oooooooo offset within the target code segment 31..16
*segment register, in protected mode
0 nnnnnnnn nnnnn... table entry number
........ .....1.. local/global table
........ ......ll privilege level
*task state segment
*as selected by the segment descriptor pointed to by the task register
00 32bit: (0:back link),esp0,(0:ss0),esp1,(0:ss2),esp2,cr3
20 32bit: eip,eflags,eax,ecx,edx,ebx,esp,ebp
40 32bit: esi,edi,(0:es),(0:cs),(0:ss),(0:ds),(0:fs),(0:gs),
60 32bit: (0:ldt),(bit_map_offset:debug_trap bit),
68 operating system info
bit_map_offset: i/o permission bitmap up to 64kbit/8==8kbyte
ffh terminator?
*global descriptor table register (gdtr)
0 16bit: limit
2 32bit: base
*interrupt descriptor table register (idtr)
0 16bit: limit
2 32bit: base
*local descriptor table register (ldtr)
0 16bit: selector
*task register
0 16 bit: selector
*control register 0 (cr0)
*the lower half is the 80286 machine status word (msw) register
fedcba98 76543210
0 00000000 000..... must be 0
........ ..1..... handle floating point exceptions via int16/external_int
........ ...1.... must be 1
........ ....1... task switched, set by hw, (gives fault7 on fp instruction)
........ .....1.. emulate copressor via fault7
........ ......1. give fault7 on wait instruction after task switch
........ .......1 enable segment based protection mode
2 1....... ........ enable paging (may only be set in protected mode)
.00..... ........ +cache_fill +wr_through&invalidates
.01..... ........ invalid
.10..... ........ -cache_fill +wr_through&invalidates
.11..... ........ -cache_fill -wr_through&invalidates
...00000 00000.0. must be 0
........ .....1.. enable alignment check bit in eflags (486 only)
........ .......1 enable write protect from supervisor write access
*control register 2 (cr2)
fedcba98 76543210 fedcba98 76543210
0 aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa last page fault linear address
*control register 3 (cr3)
fedcba98 76543210 fedcba98 76543210
0 bbbbbbbb bbbbbbbb bbbb.... ........ base of page directory (4k aligned)
........ ........ ........ ...1.... disable page cache (486 only)
........ ........ ........ ....1... page write through (486 only)
........ ........ ....0000 000..000 must be 0
*end