8237
programmable DMA controller
register usage
19880617/wj van ganswijk

0  rw address0 (lsb first)
1  rw count0   (lsb first)
2  rw address1 (lsb first)
3  rw count1   (lsb first)
4  rw address2 (lsb first)
5  rw count2   (lsb first)
6  rw address3 (lsb first)
7  rw count3   (lsb first)

8  w  write to command register
      .......1  memory to memory enable
      ......1.  channel 0 address hold enable (if b0)
      .....1..  controller disable
      ....1...  compressed timing (if !b0)
      ...1....  rotating/fixed priority
      ..1.....  extended/late write (if !b3)
      .1......  DRQ active low/high
      1.......  DACK active high/low
   r  read status register
      .......1  channel 0 TC
      ......1.  channel 1 TC
      .....1..  channel 2 TC
      ....1...  channel 3 TC
      ...1....  channel 0 DMA request
      ..1.....  channel 1 DMA request
      .1......  channel 2 DMA request
      1.......  channel 3 DMA request
9  w  write to request register
      ......nn  channel nr (0..3)
      .....1..  set/reset request bit
      xxxxx...  not used
a  w  write a mask register bit
      ......nn  channel nr (0..3)
      .....1..  set/reset mask bit
      xxxxx...  not used
b  w  write to mode register
      ......nn  channel nr (0..3)
      ....00..  verify (with memory) transfer (if b6b7!=11)
      ....01..  write  (to   memory) transfer (if b6b7!=11)
      ....10..  read   (from memory) transfer (if b6b7!=11)
      ....11..  illegal
      ...1....  enable autoinitialize
      ..1.....  address decrement
      00......  demand mode
      01......  single mode
      10......  block mode
      11......  cascade mode
c  w  clear byte pointer flip-flop
d  r  read temporary register (last byte transported)
   w  master clear
e  w  clear mask register, dwz sta drq's toe
f  w  write all mask register bits
      .......1  set/clear channel 0 mask bit
      ......1.  set/clear channel 1 mask bit
      .....1..  set/clear channel 2 mask bit
      ....1...  set/clear channel 3 mask bit
      xxxx....  not used

*end