*8250 *asynchronous communication element (ACE) *amongst others from Samsung *originally probably from UMC *19891115/wjvg 0 rbr/thr = receiver buffer register/transmitter holder register 1 ier = interrupt enable register rw .......1 enable received data available interrupt rw ......1. enable transmitter holding register empty interrupt rw .....1.. enable receiver line status interrupt rw ....1... enable modem status interrupt r 0000.... not used 2 iir = interrupt identification register (r) r .......0 interrupt pending/not r .....00. interrupt from modem logic r .....01. interrupt from transmitter r .....10. interrupt from receiver r .....11. interrupt from error logic r 00000... not used 3 lcr = line control register rw ......00 nr of data bits = 5 rw ......01 nr of data bits = 6 rw ......10 nr of data bits = 7 rw ......11 nr of data bits = 8 rw .....0.. nr of stopbits = 1 rw .....1.. nr of stopbits = 1.5 if 5 data bits else 2 if 6,7 or 8 data bits rw ...x0... no parity rw ...01... odd parity rw ...11... even parity rw ..1..... stick parity rw .1...... break enabled rw 1....... divisor latch access bit 4 mcr = modem control register rw .......1 data terminal ready rw ......1. request to send rw .....1.. out1 (inverted to output) rw ....1... out2 (inverted to output) (pc: interrupt enable) rw ...1.... loop enabled r 000..... not used 5 lsr = line status register rw .......1 data ready rw ......1. overrun error rw .....1.. parity error rw ....1... framing error rw ...1.... break interrupt rw ..1..... transmitter holding register empty (gebruik deze!) rw .1...... transmitter shift register empty r 0....... not used (in het echt 1!) 6 msr = modem status register rw .......1 delta clear to send rw ......1. delta data set ready rw .....1.. trailing edge ring indicator rw ....1... delta data carrier detect rw ...1.... clear to send rw ..1..... data set ready rw .1...... ring indicator rw 1....... data carrier detect 7 scr = scratch register rw nnnnnnnn may be used freely, has no effect if b7 of lcr is set: 0 dll = divisor latch (lsb) external freq is predivided by 16 1 dlm = divisor latch (msb) *end